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IS61NLP25632 Datasheet PDF - Integrated Silicon Solution

Part NameDescriptionManufacturer
IS61NLP25632 256K x 32, 256K x 36 and 512K x 18 PIPELINE 'NO WAIT' STATE BUS SRAM ISSI
Integrated Silicon Solution ISSI
Other PDF  no available.
IS61NLP25632 Datasheet PDF : IS61NLP25632 pdf   
IS61NLP25636 image

DESCRIPTION
The 8 Meg NP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for network and communications customers. They are organized as 262,144 words by 32 bits, 262,144 words by 36 bits and 524,288 words by 18 bits, fabricated with ISSIs advanced CMOS technology.

FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining for TQFP
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119 PBGA package
• Single +3.3V power supply (± 5%)
• NP Version: 3.3V I/O Supply Voltage
• NLP Version: 2.5V I/O Supply Voltage
• Industrial temperature available

 

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