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IS61NLP25636A Datasheet PDF - Integrated Silicon Solution

Part NameDescriptionManufacturer
IS61NLP25636A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI
Integrated Silicon Solution ISSI
Other PDF  no available.
IS61NLP25636A Datasheet PDF : IS61NLP25636A pdf   
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The 9 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSIs advanced CMOS technology.

• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
• Power supply:
    NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
    NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available


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